1. Field of the Invention
This invention generally relates to a semiconductor device and manufacturing method thereof, and especially to a semiconductor device having self-aligned contact and manufacturing method thereof.
2. Description of Related Art
Along with technical progress of semi-conductor technology, the sizes of the devices decrease gradually and enter into the deep submicron level. Recent manufacture process of ultra large integrated circuit (ULSI) has been developed to the extent of less than 0.18 micrometers. Along with increase of the integration of the integrated circuits, the contact between the metal and the semiconductor become smaller gradually. In order to overcome the gradually smaller line width and prevent the misalignment of the contacts, the design with self-aligned contact (i.e. SAC) is utilized generally.
FIG. 1 is a drawing, schematically showing a top view of a conventional semiconductor device 100 having self-aligned contacts. FIG. 2A to 2D are drawings, schematically showing cross-sectional views of a manufacturing process along the I-I line at the X direction in FIG. 1. FIG. 3A to 3D are drawings, schematically showing cross-sectional views of the manufacturing process along the II-II line at the Y direction in FIG. 1. The conventional method of manufacturing semiconductor devices having self-aligned contacts is described as below.
First, as shown in FIG. 1, FIG. 2A and FIG. 3A at the same time, multiple shallow trench isolation structures 104 are formed in the substrate 102 to define an active area 101. The manufacturing process of the shallow trench isolation structures 104 is described as below.
FIGS. 4A to 4E are drawings, schematically showing cross-sectional views of a manufacturing process of the shallow trench isolation structures along the I-I line at the X direction in FIG. 1. First, as shown in FIG. 4A, a patterned under-layer 103 and a patterned mask layer 105 are formed on the substrate 102 to expose a portion of the substrate 102, wherein the total thickness of the patterned under-layer 103 and the patterned mask layer 105 is greater than 1000 angstroms. Further, as shown in FIG. 4B, with the patterned under-layer 103 and the patterned mask layer 105 as the mask, the exposed portion of the substrate 102 is removed to form multiple trenches 107 in the substrate 102. Further, as shown in FIG. 4C, a silicon oxide isolation material layer 109 is formed over the substrate 102 to cover the patterned mask layer 105 and to fully fill the trenches 107. In addition, as shown in FIG. 4D, a portion of the isolation material layer 109 outside the trenches 107 is removed. Furthermore, as shown in FIG. 4E, the patterned mask layer 105 and the patterned under-layer 103 are removed, and the isolation material layer 109 is etched by HF acid, until the thickness of the isolation material is about 300 angstroms to 400 angstroms.
Further continually as shown in FIG. 1, FIG. 2A and FIG. 3A, after the shallow trench isolation structures 104 are formed, multiple gate structures 106 are formed on the substrate 102. The gate structures 106 include the underneath disposed gate dielectric layer 108 and the upper disposed gate layer 110. Further, multiple doped areas 114 are formed in the substrate 102 at side of the each gate structure 106. Furthermore, multiple spacers 112 are formed on the sidewall of the each gate structure 106.
Further, as shown in FIG. 1, FIG. 2B and FIG. 3B, the silicon nitride layer 116 is formed on the substrate 102, for covering the substrate 102, the shallow trench isolation structures 104, each of the gate structure 106 and each of the spacers 112. Furthermore, the silicon oxide inter-layering dielectric layer 118 (ILD) is formed on the silicon nitride layer 116.
Further, as shown in FIG. 1, FIG. 2C and FIG. 3C, a self-aligned process is performed to form multiple contact openings 120 in the inter-layering dielectric layer 118 between the neighboring gate structures 106, for exposing the doped areas 114. The material of the inter-layering dielectric layer 118 is the same as the material of the shallow trench isolation structures 104. In this situation, in order to avoid damage to the shallow trench isolation structures 104 during forming the contact openings 120, the above mentioned silicon nitride layer 116 can be treated as an etching mask layer at the self-aligned process. As for the details, during forming the contact openings 120, a first etching process can be performed at the inter-layering dielectric layer 118 and the etching process can stop at the silicon nitride layer 116. Further, a cleaning process is performed. Even furthermore, another etching process can be performed at the silicon nitride layer 116 again to accomplish the manufacture of the contact openings 120.
Further, as shown in FIG. 1, FIG. 2D and FIG. 3D, a conductive material is filled in each of the contact opening 120. Furthermore, the superabundant conductive material is removed for forming the plug structures 122, and a semiconductor device having self-aligned contacts 100 is accomplished.
It should be noted that although the damage to the shallow trench isolation structures can be avoided by forming the silicon nitride at the self-aligned process, the necessary integration of the device itself must be sacrificed in order to form the silicon nitride layer. Furthermore, when the distance between the neighboring shallow trench isolation structures becomes smaller and smaller, the holes may be formed between the shallow trench isolation structures at forming the silicon nitride layer. Therefore, even though the manufacture process technology can achieve a success to a further smaller line width, the relative large preserved space in advance between the shallow trench isolation structures is still necessary, in order to prevent the holes from being caused. As a result, the improvement of the integration of the device is affected.